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? 2008-2013 microchip technology inc. ds80369p-page 1 pic24fj256gb110 family the pic24fj256gb110 family devices that you have received conform functionally to the current device data sheet (ds39897 c ), except for the anomalies described in this document. the silicon issues discussed in the following pages are for silicon revisions with the device and revision ids listed in ta bl e 1 . the silicon issues are summarized in table 2 . the errata described in this document will be addressed in future revisions of the pic24fj256gb110 family silicon. data sheet clarifications and corrections start on page 14 , following the discussion of silicon issues. the silicon revision level can be identified using the current version of mplab ? ide and microchip?s programmers, debuggers and emulation tools, which are available at the microchip corporate web site ( www.microchip.com ). for example, to identify the silicon revision level using mplab ide in conjunction with mplab icd 2 or pickit? 3: 1. using the appropriate interface, connect the device to the mplab icd 2 programmer/debugger or to the pickit 3. 2. from the main menu in mplab ide, select configure>select device , and then select the target part number in the dialog box. 3. select the mplab ide hardware tool ( debugger>select tool ). 4. perform a ?connect? operation to the device ( debugger>connect ). depending on the devel- opment tool used, the part number and device revision id value appear in the output window. the devrev values for the various pic24fj256gb110 family silicon revisions are shown in table 1 . note: this document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. only the issues indicated in the last column of table 2 apply to the current silicon revision ( a6 ). note: if you are unable to extract the silicon revision level, please contact your local microchip sales office for assistance. table 1: silicon devrev values part number device id ( 1 ) revision id for silicon revision ( 2 ) part number device id ( 1 ) revision id for silicon revision ( 2 ) a3 a5 a6 a3 a5 a6 pic24fj256gb110 101fh 01h 03h 04h pic24fj128gb108 100bh 01h 03h 04h pic24fj192gb110 1017h pic24fj64gb108 1003h pic24fj128gb110 100fh pic24fj256gb106 1019h pic24fj64gb110 1007h pic24fj192gb106 1011h pic24fj256gb108 101bh pic24fj128gb106 1009h pic24fj192gb108 1013h pic24fj64gb106 1001h note 1: the device ids (devid and devrev) are located at the last two implemented addresses of configuration memory space. they are shown in hexadecimal in the format, ?devid devrev?. 2: refer to the ?pic24fjxxxga0xx flash programming specification? (ds39768) for detailed information on device and revision ids for your specific device. pic24fj256gb110 family silicon errata and data sheet clarification
pic24fj256gb110 family ds80369p-page 2 ? 2008-2013 microchip technology inc. table 2: silicon issue summary module feature item number issue summary affected revisions ( 1 ) a3 a5 a6 core ram operation 1. repeated register operations entering doze mode. x x x core bor 2. spontaneous bor with analog or usb peripherals. x jtag device programming 3. programming lockout during jtag programming. x x x uart ? 4. framing issues when using two stop bits. x i/o portb 5. rb5 remains in high-impedance in open-drain mode. x spi master mode 6. spixif and spirbf may be set early in some instances. x ctmu ? 7. trigger to ic or oc modules may not work. x usb ? 8. issue with host mode, low-speed operation. x x x usb v usb regulator 9. does not regulate to 3.3v. x x x usb ? 10. crc errors while using external transceiver. x x x usb ? 11. activif flag functions only during sleep. x x x uart uerif interrupt 12. interrupt may not function with multiple errors. x uart fifo error 13. perr and ferr flags may be incorrect in certain cases. x uart irda ? 14. payload error in 8-bit mode. x uart irda 15. framing error in 9-bit mode. x uart irda 16. payload errors in 8-bit mode. x i 2 c? module master mode 17. master module may acknowledge its own transmission as a slave. x i 2 c module slave mode 18. module may not respond correctly to reserved addresses. x memory psv 19. false address error traps. x icsp? ? 20. pgec3/pged3 not functional. x core instruction set 21. issue with read-after-write stalls in repeat loops. x x x rtcc ? 22. unexpected decrements of alarm repeat counter. x spi enhanced buffer mode 23. issue with early full buffer interrupt. x a/d ? 24. disabled voltage references during debug mode (64-pin devices only). x spi enhanced buffer mode 25. issue with srmpt bit becoming set early in certain cases. x core code-protect 26. gcp disables write access to interrupt vectors. x ctmu a/d trigger 27. automatic conversion may not function. x oscillator lprc 28. failure to restart following bor events. x oscillator two-speed start-up 29. feature is not functional. x x x output compare ? 30. single missed compare events under certain conditions. x interrupts intx 31. external interrupts missed when writing to intcon2. x x x a/d converter ? 32. module continues to draw current when disabled. x x x note 1: only those issues indicated in the last column apply to the current silicon revision.
? 2008-2013 microchip technology inc. ds80369p-page 3 pic24fj256gb110 family oscillator ? 33. poscen bit does not work with primary + pll modes. xxx output compare interrupt 34. interrupt flag may precede the output pin change under certain circumstances. xxx ctmu ? 35. disabling module affects band gap. x x x uart transmit 36. a tx interrupt may occur before the data transmission is complete. xxx usb device mode 37. epstall bit behavior differs from previous documentation. xxx usb device and host modes 38. actvif wake-up behavior differs from previous documentation. xxx table 2: silicon issue summary (continued) module feature item number issue summary affected revisions ( 1 ) a3 a5 a6 note 1: only those issues indicated in the last column apply to the current silicon revision.
pic24fj256gb110 family ds80369p-page 4 ? 2008-2013 microchip technology inc. silicon errata issues 1. module: core (ram operation) if a ram read is performed on the instruction immediately prior to enabling doze mode, an extra read event may occur when doze mode is enabled. this has no effect on most sfrs and on user ram space. however, this could cause regis- ters which also perform some action on a read (such as auto-incrementing a pointer or removing data from a fifo buffer) to repeat that action, possibly resulting in lost data or unexpected operation. work around avoid reading registers which perform a second- ary action (e.g., uartx and spix?s fifo buffers, and the rtcval registers) immediately prior to entering doze mode. if this cannot be avoided, execute a nop instruction before entering doze mode. affected silicon revisions 2. module: core (bor) when the on-chip regulator is enabled (envreg tied to v dd ), a bor event may spontaneously occur under the following circumstances: ?v dd is less than 2.5v, and either: ? the internal band gap reference is being used as a reference with the a/d converter (ad1pcfg2<1> or <0> = 1 ) or comparators (cmxcon<1:0> = 11 ); or ? the ctmu or the usb module is enabled. work around limit the following activities to only those times when the on-chip regulator is not in tracking mode (lvdif (ifs4<8>) = 0 ): ? enabling the usb or ctmu modules ? selecting the internal band gap as a reference for the a/d converter or the comparators affected silicon revisions 3. module: jtag (device programming) the jtagen configuration bit can be pro- grammed to ? 0 ? while using the jtag interface for device programming. this may cause a situation where jtag programming can lock itself out of being able to program the device. work around none. affected silicon revisions 4 module: uart when the uartx is operating using two stop bits (stsel = 1 ), it may sample the first stop bit instead of the second one. if the device being communicated with is one using one stop bit in its communications, this may lead to framing errors. work around none. affected silicon revisions 5. module: i/o (portb) when rb5 is configured as an open-drain output, it remains in a high-impedance state. the settings of latb5 and trisb5 have no effect on the pin?s state. work around if open-drain operation is not required, configure rb5 as a regular i/o (odcb<5> = 0 ). if open-drain operation is required, there are two options: ? select a different i/o pin for the open-drain function ? place an external transistor on the pin and configure the pin as a regular i/o affected silicon revisions note: this document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. only the issues indicated by the shaded column in the following tables apply to the current silicon revision ( a6 ). a3 a5 a6 xx x a3 a5 a6 xx x a3 a5 a6 xx x a3 a5 a6 x a3 a5 a6 x
? 2008-2013 microchip technology inc. ds80369p-page 5 pic24fj256gb110 family 6. module: spi (master mode) in master mode, both the spix interrupt flag (spixif) and the spirbf bit (spixstat<0>) may become set one-half clock cycle early, instead of on the clock edge. this occurs only under the following circumstances: ? enhanced buffer mode is disabled (spiben = 0 ) ? the module is configured for serial data output changes on transition from clock active to clock idle state (cke = 1 ) if the application is using the interrupt flag to deter- mine when data to be transmitted is written to the transmit buffer, the data currently in the buffer may be overwritten. work around before writing to the spix buffer, check the sckx pin to determine if the last clock edge has passed. example 1 (below) demonstrates a method for doing this. in this example, pin, rd1, functions as the spix clock, sckx, which is configured as idle low. affected silicon revisions 7. module: ctmu when the ctmu module is selected as the trigger source (syncsel<4:0> = 11000 ), the output compare or input capture module triggers may not work. work around manually trigger the output compare and/or input capture modules after a ctmu event is received. be certain to compensate for any time latency required by manually triggering the module. affected silicon revisions 8. module: usb while operating in host mode and attached to a low-speed device through a full-speed usb hub, the pre signal may not be generated correctly. this will result in not being able to communicate correctly with the low-speed device. work around connect low-speed devices directly to the application and not through a usb hub. affected silicon revisions 9. module: usb (v usb regulator) the usb internal voltage regulator does not regulate to 3.3v. the usb internal voltage regulator is an optional feature and is not required for usb operation or compliance. work around disable the usb voltage regulator (disuvreg configuration bit set to ? 1 ?) and supply 3.0v to 3.6v from an external source to the v usb pin. affected silicon revisions 10. module: usb when the module is configured to use an external transceiver, the crc5 value of some packets may be incorrect. work around use the module?s internal transceiver. affected silicon revisions example 1: checking the state of spixif against the spix clock a3 a5 a6 x a3 a5 a6 x a3 a5 a6 xx x a3 a5 a6 xx x a3 a5 a6 xx x while(ifs0bits.spi1if == 0){} //wait for the transmission to complete while(portdbits.rd1 == 1){} //wait for the last clock to finish spi1buf = 0xff; //write new data to the buffer
pic24fj256gb110 family ds80369p-page 6 ? 2008-2013 microchip technology inc. 11. module: usb the bus activity interrupt flag, actvif, is active only while the device is in sleep mode. it will not become set when the microcontroller is in a run mode. work around the type of work around depends on the type of application that the microcontroller is being used for. for self-powered peripherals: after receiving a suspend command from the pc, do not suspend or disable the usb module. in addition, do not switch to a clock configuration that is incompatible with usb operation (refer to the device data sheet for usb compatible clock settings). for bus powered peripherals: after receiving a suspend command from the pc (idleif interrupt flag = 1 ): ? suspend the usb module (u1pwrc<1> = 1 ) ? globally enable usb interrupts (iec5<6> = 1 ) ? specifically enable the bus activity interrupt (u1otgie<4> = 1 ) ? place the microcontroller into sleep mode as soon as possible for embedded host devices: ? issue a suspend command to the peripheral device ? suspend the usb module (u1pwrc<1> = 1 ) ? globally enable usb interrupts (iec5<6> = 1 ) ? place the microcontroller into sleep mode as soon as possible as an alternate procedure, do not suspend or disable the usb module and do not switch to a clock configuration that is incompatible with usb operation. affected silicon revisions 12. module: uart (uerif interrupt) the uartx error interrupt may not occur, or occur at an incorrect time, if multiple errors occur during a short period of time. work around read the error flags in the uxsta register when- ever a byte is received to verify the error status. in most cases, these bits will be correct, even if the uartx error interrupt fails to occur. for possible exceptions, refer to errata # 13. affected silicon revisions 13. module: uart (fifo error flags) under certain circumstances, the perr and ferr error bits may not be correct for all bytes in the receive fifo. this has only been observed when both of the following conditions are met: ? the uartx receive interrupt is set to occur when the fifo is full or ? full (uxsta<7:6> = 1x ) ? more than 2 bytes with an error are received in these cases, only the first two bytes with a parity or framing error will have the corresponding bits indicate correctly. the error bits will not be set after this. work around none. affected silicon revisions 14. module: uart (irda ? ) when the uartx is operating in 8-bit mode (pdsel<1:0> = 0x ) and using the irda endec (iren = 1 ), the module incorrectly transmits a data payload of 80h as 00h. work around none. affected silicon revisions a3 a5 a6 xx x a3 a5 a6 x a3 a5 a6 x a3 a5 a6 x
? 2008-2013 microchip technology inc. ds80369p-page 7 pic24fj256gb110 family 15. module: uart (irda) when the uartx is operating in 8-bit mode (pdsel<1:0> = 0x ) and using the irda endec (iren = 1 ), a framing error may occur when transmitting a data payload of 00h. work around : none. affected silicon revisions 16. module: uart (irda) when the uartx is operating in 9-bit mode (pdsel<1:0> = 1x ) and using the irda endec (iren = 1 ), the module will incorrectly transmit 10 bits when transmitting data payloads of 00h or 80h. work around : none. affected silicon revisions 17. module: i 2 c? module (master mode) under certain circumstances, a module operating in master mode may acknowledge its own com- mand addressed to a slave device. this happens when the following occurs: ? 10-bit addressing mode is used (a10m = 1 ) ?the i 2 c master has the same two upper address bits (i2cadd<9:8>) as the addressed slave module in these cases, the master also acknowledges the address command and generates an erroneous i 2 c slave interrupt, as well as the i 2 c master interrupt. work around several options are available: ? when using 10-bit addressing mode, make certain that the master and slave devices do not share the same 2 msbs of their addresses. if this cannot be avoided: ? clear the a10m bit (i2cxcon<10> = 0 ) prior to performing a master mode transmit. ? read the add10 bit (i2cxstat<8>) to check for a full 10-bit match whenever a slave i 2 c interrupt occurs on the master module. affected silicon revisions 18. module: i 2 c module (slave mode) under certain circumstances, a module operating in slave mode, may not respond correctly to some of the special addresses reserved by the i 2 c protocol. this happens when the following occurs: ? 10-bit addressing mode is used (a10m = 1 ) ? bits, a<7:1>, of the slave address (i2cadd<7:1>) fall into the range of the reserved 7-bit address ranges: ? 1111xxx ? or ? 0000xxx ?. in these cases, the slave module acknowledges the command and triggers an i 2 c slave interrupt; it does not copy the data into the i2cxrcv register or set the rbf bit. work around do not set bits, a<7:1>, of the module?s slave address equal to ? 1111xxx ? or ? 0000xxx ?. affected silicon revisions a3 a5 a6 x a3 a5 a6 x a3 a5 a6 x a3 a5 a6 x
pic24fj256gb110 family ds80369p-page 8 ? 2008-2013 microchip technology inc. 19. module: memory (program space visibility) when accessing data in the psv area of data ram, it is possible to generate a false address error trap condition by reading data located pre- cisely at the lower address boundary (8000h). if data is read using an instruction with an auto-decrement, the resulting ram address will be below the psv boundary (i.e., at 7ffeh); this will result in an address error trap. this false address error can also occur if a 32-bit mov instruction is used to read the data at location, 8000h. work around do not use the first location of the psv page (address 8000h). the mplab c compiler (v3.11 or later) supports the option, ? -merrata=psv_trap ?, to prevent it from generating code that would cause this erratum. affected silicon revisions 20. module: icsp? the icsp/icd port pair, pgec3/pged3 (rb5/rb4), cannot be used to read or program the device. work around use either pgec2/pg ed2 or pgec1/pged1. affected silicon revisions 21. module: core (instruction set) if an instruction producing a read-after-write stall condition is executed inside a repeat loop, the instruction will be executed fewer times than was intended. for example, this loop: repeat #0xf inc [w1],[++w1] will execute less than 15 times. work around avoid using repeat to repetitively execute instructions that create a stall condition. instead, use a software loop using conditional branches. the mplab c compiler will not generate repeat loops that cause this erratum. affected silicon revisions 22. module: rtcc under certain circumstances, the value of the alarm repeat counter (alcfgrpt<7:0>) may be unexpectedly decremented. this happens only when a byte write to the upper byte of alcfgrpt is performed in the interval between a device por/bor, and the first edge from the rtcc clock source. work around do not perform byte writes on alcfgrpt, particularly the upper byte. alternatively, wait until one period of the sosc has completed before performing byte writes to alcfgrpt. affected silicon revisions a3 a5 a6 x a3 a5 a6 x a3 a5 a6 xx x a3 a5 a6 x
? 2008-2013 microchip technology inc. ds80369p-page 9 pic24fj256gb110 family 23. module: spi (enhanced buffer modes) if the spix event interrupt is configured to occur when the enhanced fifo buffer is full (sisel<2:0> = 111 ), the interrupt may actually occur when the 7th byte is written to the buffer, instead of the 8th byte. the other enhanced buffer interrupts function as previously described. work around do not use the full buffer interrupt mode. the spitbf bit (spixstat<1>) reliably indicates when the enhanced fifo buffer is full and can be polled instead of using the full buffer interrupt mode. affected silicon revisions 24. module: a/d converter when using pgec1 and pged1 to debug an application on any 64-pin devices in this family, all voltage references will be disabled. this includes v ref +, v ref -, av dd and av ss . any a/d conversion will always equal 0x3ff. work around use pgec2 and pged2 to debug any a/d functionality. affected silicon revisions 25. module: spi (enhanced buffer mode) in enhanced master mode, the srmpt bit (spixstat<7>) may erroneously become set for several clock cycles in the middle of a fifo transfer, indicating that the shift register is empty when it is not. this happens when both spix clock prescalers are set to values other than their maximum (spixcon<4:2> 000 and spixcon<1:0> 00 ). work around set sisel<2:0> (spixstat<4:2>) to ? 101 ?. this configures the module to generate an spix event interrupt whenever the last bit is shifted out of the shift register. when the spixif flag becomes set, the shift register is empty. affected silicon revisions 26. module: core (code protection) when general segment code protection has been enabled (gcp configuration bit is programmed), applications are unable to write to the first 512 bytes of the program memory space (0000h through 0200h). in applications that may require the interrupt vectors to be changed during run time, such as bootloaders, modifications to the interrupt vector tables (ivt) will not be possible. work around create two new interrupt vector tables, one each for the ivt and aivt, in an area of program space beyond the affected region. map the addresses in the old vector tables to the new tables. these new tables can then be modified as needed to the actual addresses of the isrs. affected silicon revisions 27. module: ctmu (a/d trigger) the ctmu may not trigger an automatic a/d con- version after the current source is turned off. this happens even when the a/d trigger control bit, cttrig (ctmucon<8>), has been set. work around perform a manual a/d conversion by clearing the samp bit (ad1con1<1>) immediately after the ctmu current source has been stopped. affected silicon revisions a3 a5 a6 x note: this issue only applies to 64-pin devices in this family (pic24fj256gb106, pic24fj192gb106, and pic24fj64gb106). a3 a5 a6 x a3 a5 a6 x a3 a5 a6 x a3 a5 a6 x
pic24fj256gb110 family ds80369p-page 10 ? 2008-2013 microchip technology inc. 28. module: oscillator (lprc) the lprc may not automatically restart following bor events (i.e., when supply voltage sags to between the bor and por thresholds, then returns to above the bor level). when this happens, systems that use the lprc clock may not work. this includes the pll, two-speed start-up, fail-safe clock monitor and the wdt. work around for pll issues: select a non-pll clock mode as the initial start-up mode, using the fnosc config- uration bits (cw2<10:8>). after the application has initialized, switch to a pll clock mode in software using the nosc bits (osccon<10:8>). allow 10 ? s to elapse between application start-up and a software clock switch. for wdt issues: disable the wdt by program- ming the fwdten bit (cw1<7>). after the application has initialized, enable the wdt in soft- ware by setting the swdten bit (rcon<5>). allow 10 ? s to elapse between application start-up and setting swdten. affected silicon revisions 29. module: oscillator (two-speed start-up) two-speed start-up is not functional. leaving the ieso configuration bit in its default state (two-speed start-up enabled) may result in unpredictable operation. work around none. always program the ieso configuration bit to disable the feature (cw2<15> = 0 ). affected silicon revisions 30. module: output compare in pwm mode, the output compare module may miss a compare event when the current duty cycle register (ocxrs) value is 0000h (0% duty cycle) and the ocxrs register is updated with a value of 0001h. the compare event is only missed the first time a value of 0001h is written to ocxrs and the pwm output remains low for one pwm period. subsequent pwm high and low times occur as expected. work around if the current ocxrs register value is 0000h, avoid writing a value of 0001h to ocxrs. instead, write a value of 0002h. in this case, however, the duty cycle will be slightly different from the desired value. affected silicon revisions 31. module: interrupts (intx) writing to the intcon2 register may cause an external interrupt event (inputs on int0 through int4) to be missed. this only happens when the interrupt event and the write event occur during the same clock cycle. work around if this cannot be avoided, write the data intended for intcon2 to any other register in the interrupt block of the sfr (addresses, 0080h to 00e0h); then write the data to intcon2. be certain to write the data to a register not being actively used by the application, or to any of the interrupt flag registers, in order to avoid spurious interrupts. for example, if the interrupts controlled by iec5 are not being used in the application, the code sequence would be: iec5 = 0x1e; intcon2 = 0x1e; iec5 = 0; it is the user?s responsibility to determine an appropriate register for the particular application. affected silicon revisions a3 a5 a6 x a3 a5 a6 xx x a3 a5 a6 xx x a3 a5 a6 xx x
? 2008-2013 microchip technology inc. ds80369p-page 11 pic24fj256gb110 family 32. module: a/d converter once the a/d module is enabled (ad1con1<15> = 1 ), it may continue to draw extra current, even if the module is later disabled (ad1con1<15> = 0 ). work around in addition to disabling the module through the adon bit, set the corresponding pmd bit (adc1md, pmd1<0>) to power it down completely. disabling the a/d module through the pmd regis- ter also disables the ad1pcfg registers, which in turn affects the state of any port pins with analog inputs. users should consider the effect on i/o ports and other digital peripherals on those ports when adc1md is used for power conservation. affected silicon revisions 33. module: oscillator the poscen bit (osccon<2>) has no effect when a primary oscillator with pll mode is selected (cosc<2:0> = 011 ). if xtpll, hspll or ecpll oscillator mode are selected, and the device enters sleep mode, the primary oscilla- tor will be disabled, regardless of the state of the poscen bit. xt, hs and ec oscillator modes (without the pll) will continue to operate as expected. work around none. affected silicon revisions 34. module: output compare (interrupt) under certain circumstances, an output com- pare match may cause the interrupt flag (ocxif) to become set prior to the change-of-state (cos) of the ocx pin. this has been observed when all of the following are true: ? the module is in one-shot mode (ocm<2:0> = 001 , 010 or 100 ); ? one of the timer modules is being used as the time base; and ? a timer prescaler other than 1:1 is selected. if the module is re-initialized by clearing ocm<2:0> after the one-shot compare, the ocx pin may not be driven as expected. work around after ocxif is set, allow an interval (in cpu cycles) of at least twice the prescaler factor to elapse before clearing ocm<2:0>. for example, for a prescaler value of 1:8, allow 16 cpu cycles to elapse after the interrupt. affected silicon revisions 35. module: ctmu using the ctmumd bit (pmd4<2>) to selec- tively power down the module may reduce the accuracy of the internal band gap reference (v bg ). in those cases where v bg is used as a reference for other analog modules, the accu- racy of measurements or comparisons may be affected. work around if the a/d converter or comparators are being used with v bg selected as a reference, do not set the ctmumd bit. affected silicon revisions a3 a5 a6 xx x a3 a5 a6 xx x a3 a5 a6 xx x a3 a5 a6 xx x
pic24fj256gb110 family ds80369p-page 12 ? 2008-2013 microchip technology inc. 36. module: uart when using utxisel<1:0> = 01 (interrupt when last character is shifted out of the transmit shift register), and the final character is being shifted out through the transmit shift register, the tx interrupt may occur before the final bit is shifted out. work around if it is critical that the interrupt processing occurs only when all transmit operations are complete, after which, the following work around can be implemented: hold off the interrupt routine processing by adding a loop at the beginning of the routine that polls the transmit shift register empty bit, as shown in example 2 . affected silicon revisions 37. module: usb (device mode) in previous literature for this module, the epstall bits (u1epn<1>) are described as being only stall status indicator bits in device mode. in actual implementation, the epstall bits function as both status and control bits. if the epstall bit for endpoint ?n? is set (either by the sie hardware or manually in firmware), both the in and out endpoints, associated with the endpoint, will send stall packets when the endpoint?s uown bit (bdnstat<15>) is also set. work around for host applications: no work around is needed as hosts do not send stall packets. for device mode applications: when it is neces- sary to stop sending stall packets on an endpoint, clear the endpoint?s respective bstall (bdnstat<10>) and epstall bits. if the application firmware was developed based on one of the examples in the microchip usb framework, this is already the default behavior of the usb stack firmware (except version 2.8); no further work around is normally needed. if a device mode application was based upon version 2.8 of the usb framework, and the application uses stall packets on any of the application endpoints (1-15), it is suggested to update the application to the latest version. affected silicon revisions example 2: delaying the isr by polling the trmt bit a3 a5 a6 xx x a3 a5 a6 xx x // in uart2 initialization code ... u2stabits.utxisel0 = 1; // set to generate tx interrupt when all u2stabits.utxisel1 = 0; // transmit operations are complete. ... u2txinterrupt(void) { while(u2stabits.trmt==0); // wait for the transmit buffer to be empty ... // process interrupt
? 2008-2013 microchip technology inc. ds80369p-page 13 pic24fj256gb110 family 38. module: usb (device and host modes) in previous literature for this module, the actvif interrupt flag (u1otgir<4>) is described as being asserted, based on state changes detected on d+, d- or v bus , when the microcontroller is in sleep mode. in actual implementation, state changes on the rf3/usbid pin also cause the actvif flag to be asserted. as a result, logic input level changes on rf3/usbid may cause actvif to be asserted, even in non-otg applications that do not use the usbid function. this may cause the microcontroller to wake up unexpectedly. work around for on-the-go (otg) based applications: no work around is needed. f or non-otg device, host or dual-role applications: if actvif is used as a wake-up source, it is recommended that the application be designed so that rf3/usbid does not see any changes while the microcontroller is in a power-saving mode. if rf3/usbid is not needed in the application, it is recommended to configure it as a digital output. if the rf3/usbid pin is configured as a digital input, ensure that the signal provider does not change the pin state while actvif is enabled as a wake-up source. if the pin is used as a general purpose input, which can change while in the usb suspend state, check the idif flag (u1otgir<7>) after waking up from an actvif event to determine if the wake-up event was caused by a state change on rf3/usbid. affected silicon revisions a3 a5 a6 xx x
pic24fj256gb110 family ds80369p-page 14 ? 2008-2013 microchip technology inc. data sheet clarifications the following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (ds39897 c ): 1. module: guidelines for getting started with 16-bit microcontrollers section 2.4 voltage regulator pins (envreg/ disvreg and v cap /v ddcore ) has been replaced with a new and more detailed section. the entire text follows: 2.4 voltage regulator pins voltage regulator pins (envreg/disvreg and v cap /v ddcore ) the on-chip voltage regulator enable/disable pin (envreg or disvreg, depending on the device family) must always be connected directly to either a supply voltage or to ground. the particular connection is determined by whether or not the regulator is to be used: ? for envreg, tie to v dd to enable the regulator, or to ground to disable the regulator ? for disvreg, tie to ground to enable the regulator or to v dd to disable the regulator refer to section 26.2 ?on-chip voltage regulator? for details on connecting and using the on-chip regulator. when the regulator is enabled, a low-esr (< 5 ? ) capacitor is required on the v cap /v ddcore pin to stabilize the voltage regulator output voltage. the v cap /v ddcore pin must not be connected to v dd and must use a capacitor of 10 f connected to ground. the type can be ceramic or tantalum. suitable examples of capacitors are shown in table 2-1 . capacitors with equivalent specifications can be used. designers may use figure 2-3 to evaluate esr equivalence of candidate devices. the placement of this capacitor should be close to v cap /v ddcore . it is recommended that the trace length not exceed 0.25 inch (6 mm). refer to section 29.0 ?electrical characteristics? for additional information. when the regulator is disabled, the v cap /v ddcore pin must be tied to a voltage supply at the v ddcore level. refer to section 29.0 ?electrical characteristics? for information on v dd and v ddcore . figure 2-3 frequency vs. esr performance for suggested v cap . note: corrections are shown in bold . where possible, the original bold text formatting has been removed for clarity. note: this section applies only to pic24fj devices with an on-chip voltage regulator. 10 1 0.1 0.01 0.001 0.01 0.1 1 10 100 1000 10,000 frequency (mhz) esr ( ? ) note: typical data measurement at 25c, 0v dc bias. table 2-1 suitable capacitor equivalents make part # nominal capacitance base tolerance rated voltage temp. range tdk c3216x7r1c106k 10 f 10% 16v -55 to +125oc tdk c3216x5r1c106k 10 f 10% 16v -55 to +85oc panasonic ecj-3yx1c106k 10 f 10% 16v -55 to +125oc panasonic ecj-4yb1c106k 10 f 10% 16v -55 to +85oc murata grm32dr71c106ka01l 10 f 10% 16v -55 to +125oc murata grm31cr61c106kc31l 10 f 10% 16v -55 to +85oc
? 2008-2013 microchip technology inc. ds80369p-page 15 pic24fj256gb110 family 2.4.1 considerations for ceramic capacitors in recent years, large value, low-voltage, surface mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. the low-esr, small physical size and other properties make ceramic capacitors very attractive in many types of applications. ceramic capacitors are suitable for use with the inter- nal voltage regulator of this microcontroller. however, some care is needed in selecting the capacitor to ensure that it maintains sufficient capacitance over the intended operating range of the application. typical low-cost 10 f ceramic capacitors are available in x5r, x7r and y5v dielectric ratings (other types are also available, but are less common). the initial toler- ance specifications for these types of capacitors are often specified as 10% to 20% (x5r and x7r), or -20%/+80% (y5v). however, the effective capacitance that these capacitors provide in an application circuit will also vary based on additional factors, such as the applied dc bias voltage and the temperature. the total in-circuit tolerance is, therefore, much wider than the initial tolerance specification. the x5r and x7r capacitors typically exhibit satisfac- tory temperature stability (ex: 15% over a wide temperature range, but consult the manufacturer?s data sheets for exact specifications). however, y5v capaci- tors typically have extreme temperature tolerance specifications of +22%/-82%. due to the extreme temperature tolerance, a 10 f nominal rated y5v type capacitor may not deliver enough total capacitance to meet minimum internal voltage regulator stability and transient response requirements. therefore, y5v capacitors are not recommended for use with the inter- nal voltage regulator if the application must operate over a wide temperature range. in addition to temperature tolerance, the effective capacitance of large value ceramic capacitors can vary substantially, based on the amount of dc voltage applied to the capacitor. this effect can be very signifi- cant, but is often overlooked or is not always documented. a typical dc bias voltage vs. capacitance graph for 16v, 10v and 6.3v rated capacitors is shown in figure 2-4 . figure 2-4 dc bias voltage vs. capacitance characteristics when selecting a ceramic capacitor to be used with the internal voltage regulator, it is suggested to select a high-voltage rating, so that the operating voltage is a small percentage of the maximum rated capacitor volt- age. for example, choose a ceramic capacitor rated at 16v for the 2.5v core voltage. suggested capacitors are shown in table 2-1 . -80 -70 -60 -50 -40 -30 -20 -10 0 10 5 1011121314151617 dc bias voltage (vdc) capacitance change(%) 01234 6789 16v capacitor 10v capacitor 6.3v capacitor
pic24fj256gb110 family ds80369p-page 16 ? 2008-2013 microchip technology inc. 2. module: electrical specifications the ?absolute maximum ratings? listed on page 311 are amended by adding the following specification: voltage on v usb with respect to v ss ................... (v ddcore ? 0.3v) to 4.0v 3. module: electrical specifications (dc characteristics) figure 29-1 (?pic24fj256gb110 family volt- age-frequency graph?) is amended by adding an additional footnote. the updated figure is shown below (changes in bold ; bold in original removed for clarity). figure 29-1: pic24f j256gb110 family voltage- frequency graph (industrial) frequency voltage (v ddcore ) ( 1 , 2 ) 3.00v 2.00v 32 mhz 2.75v 2.50v 2.25v 2.75v 16 mhz 2.25v (2) for frequencies between 16 mhz and 32 mhz, f max = (64 mhz/v) * (v ddcore ? 2v) + 16 mhz. note 1: when the voltage regulator is disabled, v dd and v ddcore must be maintained so that v ddcore ??? v dd ??? 3.6v. 2: when the usb module is enabled, v usb should be provided at 3.0v to 3.6v while v ddcore must be 2.35v. when the usb module is not enabled, the wider limits shaded in grey apply. the voltage on the v usb pin should be maintained at (v ddcore ? .3v) or greater. optionally, the pin may be left in a high-impedance state when the usb module is not in use, but doing so may result in higher i pd currents than specified. pic24fjxxxgb1xx
? 2008-2013 microchip technology inc. ds80369p-page 17 pic24fj256gb110 family 4. module: electrical specifications (dc characteristics) table 29-3 (?dc characteristics: temperature and voltage specifications?) is amended by add- ing a new specification, v usb , and an explanatory footnote. the changes are shown below in bold text (bold text in original was removed for clarity). 5. module: electrical specifications in table 29-3 (?dc characteristics: temperature and voltage specifications?), the minimum and maximum values for dc18 (bor voltage on v dd transition) are changed to 1.80v and 2.25v, respectively. the typical value remains unchanged. table 29-3: dc characteristics: temperature and voltage specifications (partial representation) dc characteristics standard operating conditions: 2.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param no. symbol characteristic min typ (1) max units conditions operating voltage v usb usb supply voltage 3.0 3.3 3.6 v usb module enabled ( 3 ) note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: this is the limit to which v dd can be lowered without losing ram data. 3: v usb should always be maintained at v dd or greater when the usb module is enabled. the v usb pin may be left in a high-impedance state when the usb module is disabled and pins, rg2 and rg3, will not be used as general purpose inputs, but doing so may result in higher i pd currents than specified.
pic24fj256gb110 family ds80369p-page 18 ? 2008-2013 microchip technology inc. 6. module: electrical specifications table 29-7 (i/o pin input specifications) is amended by the addition of the following new specifications: ? di31 (maximum load current for internal pull-up) ? di60 (injection currents) the new specifications, and accompanying new footnotes, 5 through 9, are shown below (additions in bold ; bold in existing text was removed for clarity). table 29-7: dc characteristics: i/o pin input specifications (partial presentation) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param. symbol characteristic min. typ (1) max. units conditions di31 i pu maximum load current for digital high detection with internal pull-up ??30av dd = 2.0v ??100av dd = 3.3v i icl input low injection current di60a 0 ? -5 ( 5 , 8 ) ma all pins except v dd , v ss , av dd , av ss , mclr , v cap , rb11, sosci, sosco, d+, d-, v usb and v bus i ich input high injection current di60b 0 ? +5 ( 6 , 7 , 8 ) ma all pins except v dd , v ss , av dd , av ss , mclr , v cap , rb11, sosci, sosco, d+, d-, v usb and v bus , and all 5v tolerant pins ( 7 ) ? i ict total input injection current di60c (sum of all i/o and control pins) -20 ( 9 ) ?+20 ( 9 ) ma absolute instantaneous sum of all input injection currents from all i/o pins (| i icl + | i ich |) ? ? i ict note 1: (existing footnote) 2: (existing footnote) 3: (existing footnote) 4: (existing footnote) 5: parameter characterized but not tested. 6: non-5v tolerant pins: v ih source > (v dd + 0.3), 5v tolerant pins: v ih source > 5.5v. characterized but not tested. 7: digital 5v tolerant pins cannot tolerate any ?positiv e? input injection current from input sources greater than 5.5v. 8: injection currents > | 0 | can affect the performance of all analog peripherals (e.g., a/d, comparators, internal band gap reference, etc.) 9: any number and/or combination of i/o pins not excluded under i icl or i ich conditions is permitted pro- vided the mathematical ?absolute instantaneous? sum of the input injection currents from all pins do not exceed the specified limit. characterized but not tested.
? 2008-2013 microchip technology inc. ds80369p-page 19 pic24fj256gb110 family 7. module: electrical specifications table 29-10 and table 29-11 (shown below) are added to section 28 ?electrical characteristics? , following the existing table 29-9 (program mem- ory). all subsequent tables in this section are renumbered accordingly. (bold text in these tables represents original and unmodified content.) table 29-10: comparator specifications table 29-11: comparator volt age reference specifications operating conditions: 2.0v < v dd < 3.6v, -40c < t a < +85c (unless otherwise stated) param no. symbol characteristic min typ max units comments d300 v ioff input offset voltage * ?10 30mv d301 v icm input common mode voltage * 0?v dd v d302 cmrr common mode rejection ratio * 55 ? ? db 300 t resp response time * ( 1 ) ? 150 400 ns 301 t mc 2 ov comparator mode change to output valid * ?? 10 ? s * parameters are characterized but not tested. note 1: response time measured with one comparator input at (v dd ? 1.5)/2, while the other input transitions from v ss to v dd . operating conditions: 2.0v < v dd < 3.6v, -40c < t a < +85c (unless otherwise stated) param no. symbol characteristic min typ max units comments vrd310 cv res resolution v dd /24 ? v dd /32 lsb vrd311 cvr aa absolute accuracy ? ? av dd ? 1.5 lsb vrd312 cvr ur unit resistor value (r) ? 2k ? ? vr310 t set settling time ( 1 ) ?? 10 ? s note 1: settling time measured while cvrr = 1 and cvr<3:0> bits transition from ? 0000 ? to ? 1111 ?.
pic24fj256gb110 family ds80369p-page 20 ? 2008-2013 microchip technology inc. appendix a: document revision history rev a document (2/2008) original version of this document, for silicon revision a3. includes silicon issues 1 (core, ram operation), 2 (core, bor), 3 (jtag, programming), 4 (uart), 5 (i/o, portb), 6 (spi, master mode), 7 (input capture) and 8 through 11 (usb). rev b document (7/2008) revised silicon issues 4 (uart) and 6 (spi, master mode) to reflect updated definition of issues. added to revision a3: silicon issues 12 (uart, uerif interrupt), 13 (uart, fifo error flags), 14 through 16 (uart, irda), 17 (i 2 c, master mode), 18 (i 2 c, slave mode), 19 (memory, program space visibility), 20 (icsp), 21 (core, instruction set), 22 (rtcc), 23 (spi, enhanced buffer modes) and 24 (a/d converter). rev c document (10/2008) added silicon issue 25 (spi ? enhanced buffer mode) to revision a3. rev d document (1/2009) added silicon issue 26 (core ? code protection) to revision a3. rev e document (5/2009) added silicon issues 27 (ctmu ? a/d trigger) and 28 (oscillator ? lprc) to revision a3. ported document to unified silicon errata/data sheet clarification format. rev f document (7/2009) added silicon revision a5 to document. includes exist- ing silicon issues 1 (core, ram operation), 3 (jtag, programming), 8 through 11 (usb) and 21 (core, instruction set). no additional new issues added. rev g document (02/2010) added silicon issue 29 (oscillator ? two-speed start-up) to silicon revisions a3 and a5. rev h document (06/2010) added silicon issues 30 (output compare) and 31 (interrupts ? intx) to silicon revisions a3 and a5. rev j document (07/2010) added silicon issue 32 (a/d converter) to silicon revisions a3 and a5. rev k document (09/2010) revised silicon issue 32 (a/d converter) to reflect updated definition of issues. added data sheet clarification issue 1 (guidelines for getting started with 16-bit microcontrollers). rev l document (04/2011) added data sheet clarification issues 2, 3 and 4 (electrical characteristics). no new silicon issues added. rev m document (6/2011) added silicon revision a6 to document. includes all existing silicon issues that are applicable to silicon revi- sion a5 (issues 1, 3, 8, 9, 10, 11, 21, 29, 31 and 32). no additional new issues added. rev n document (11/2011) added silicon issues 33 (oscillator), 34 (output compare ? interrupt), 35 (ctmu), 36 (uart), 37 (usb ? device mode) and 38 (usb ? device and host modes). added data sheet clarification issues 5, 6 and 7 (electrical specifications). rev p document (1/2013) revised data sheet clarification 5 to show bor min value as 1.80v instead of 1.90v.
? 2008-2013 microchip technology inc. ds80369p-page 21 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2008-2013, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-62076-944-7 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification contai ned in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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